Parameterizable Decision Tree Classifier on NetFPGA

Machine learning approaches based on decision trees (DTs) have been proposed for classifying networking traffic. Although this technique has been proven to have the ability to classify encrypted and unknown traffic, the software implementation of DT cannot cope with the current speed of packet traffic. In this paper, hardware architecture of decision tree is proposed on NetFPGA platform. The proposed architecture is fully parameterizable to cover wide range of applications. Several optimizations have been done on the DT structure to improve the tree search performance and to lower the hardware cost. The optimizations proposed are: a) node merging to reduce the computation latency, b) limit the number of nodes in the same level to control the memory usage, and c) support variable throughput to reduce the hardware cost of the tree.